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| mos integrated circuit data sheet m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 4-bit single-chip microcomputer the m pd75068 is a member of the 75x series of 4-bit single-chip microcomputers. the minimum instruction execution time of the m pd75068's cpu is 0.95 m s. in addition to this high-speed capability, the chip contains an a /d converter and furnishes high-performance functions such as the serial bus interface (sbi) function compliant with the nec standard format, providing powerful features and high cost performance. the m pd75068(a) is a high-reliability version of the m pd75068. nec also provides prom versions suitable for small-scale production or evaluation samples in system development. the m pd75p068 is the prom version for the m pd75064, 75066, 75068, and the m pd75p068(a) is that for the m pd75064(a), 75066(a), 75068(a). the detailed function descriptions are described in the document below. please make sure to read this document before starting design. m pd75068 user's manual: ieu-1366 features ? variable instruction execution time advantageous to high-speed operation and power-saving: ? 0.95 m s, 1.91 m s, or 15.3 m s (at 4.19 mhz with the main system clock selected) ? 122 m s (at 32.768 khz with the subsystem clock selected) ? a /d converter (8-bit resolution, successive approximation): 8 channels ? capable of low-voltage operation: v dd = 2.7 to 6.0 v ? timer function: 3 channels ? on-chip nec standard serial bus interface (sbi) ? very low-power watch operation enabled (5 m a typ. at 3 v) ? pull-up resistor option allowed for 27 i/o lines ? the m pd75p068 and 75p068(a) (prom versions) available: capable of low-voltage operation (v dd = 2.7 to 6.0 v) applications ? m pd75064, 75066, 75068 home electronic appliances, air conditioners, cameras, and electronic measuring instruments ? m pd75064(a), 75066(a), 75068(a) automotive electronics the mark h shows revised points . the information in this document is subject to change without notice. document no. ic-3140b ( o.d. no. ic-8629b) date published december 1994 p printed in japan h nec corporation 1993
2 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) part number m pd75064 m pd75064(a) m pd75066 m pd75066(a) parameter m pd75068 m pd75068(a) quality grade standard special ordering information part number package quality grade m pd75064cu-xxx 42-pin plastic shrink dip (600 mil) standard m pd75064gb-xxx-3b4 44-pin plastic qfp (10x10 mm) standard m pd75066cu-xxx 42-pin plastic shrink dip (600 mil) standard m pd75066gb-xxx-3b4 44-pin plastic qfp (10x10 mm) standard m pd75068cu-xxx 42-pin plastic shrink dip (600 mil) standard m pd75068gb-xxx-3b4 44-pin plastic qfp (10x10 mm) standard m pd75064cu(a)-xxx 42-pin plastic shrink dip (600 mil) special m pd75064gb(a)-xxx-3b4 44-pin plastic qfp (10x10 mm) special m pd75066cu(a)-xxx 42-pin plastic shrink dip (600 mil) special m pd75066gb(a)-xxx-3b4 44-pin plastic qfp (10x10 mm) special m pd75068cu(a)-xxx 42-pin plastic shrink dip (600 mil) special m pd75068gb(a)-xxx-3b4 44-pin plastic qfp (10x10 mm) special remark xxx : rom code suffix please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. difference between m pd7506x subseries and m pd7506x(a) subseries h h h h h h the m pd75064, 75066, 75068 and m pd75064(a), 75066(a), 75068(a) differ only in their quality grade. unless otherwise specified, this data sheet describes the m pd75068 as the representative product. for products with the suffix (a) attached, please make the following substitutions when reading: m pd75064 > m pd75064(a) m pd75066 > m pd75066(a) m pd75068 > m pd75068(a) h 3 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) function overview item function instruction execution time ? main system clock : 0.95 m s, 1.91 m s, 15.3 m s (at 4.19 mhz) ? subsystem clock : 122 m s (at 32.768 khz) internal memory rom ? m pd75064 : 4096 8 bits ? m pd75066 : 6016 8 bits ? m pd75068 : 8064 8 bits ram 512 4 bits general register ? when operating in 4 bits: 8 ? when operating in 8 bits: 4 i/o port 32 12 cmos input of these, seven with software-specifiable on-chip pull-up resistors 12 cmos i/o software-specifiable on-chip pull-up resistors four pins can directly drive leds. 8 n-ch open-drain i/o breakdown voltage: 10 v mask-option-specifiable on-chip pull-up resistors can directly drive leds. timer 3 chs. ? timer/event counter ? basic interval timer : applicable to watchdog timer ? watch timer : capable of buzzer output serial interface ? 3-wire serial i/o mode ? 2-wire serial i/o mode ? sbi mode bit sequencial buffer 16 bits clock output function f , f x /2 3 , f x /2 4 , f x /2 6 (main system clock: at 4.19 mhz operation) a/d converter ? 8-bit resolution x 8 channels ? low-power operation possible : v dd = 2.7 to 6.0 v vectored interrupt external : 3 , internal : 3 test input external : 1, internal : 1 system clock oscillator ? ceramic/crystal oscillator for main system clock ? crystal oscillator for subsystem clock standby function stop / halt mode operating ambient C40 to +85 c temperature operating supply 2.7 to 6.0 v voltage package ? 42-pin plastic shrink dip (600 mil) ? 44-pin plastic qfp (10 x 10 mm) 4 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) contents 1. pin configuration (top view) 5 2. block diagram 7 3. pin functions 8 3.1 port pins 8 3.2 non-port pins 9 3.3 pin input/output circuits 10 3.4 mask option selection 12 3.5 handling unused pins 13 4. memory configuration 14 5. peripheral hardware functions 18 5.1 ports 18 5.2 clock generator 19 5.3 clock output circuit 20 5.4 basic interval timer 21 5.5 watch timer 22 5.6 timer/event counter 23 5.7 serial interface 24 5.8 a/d converter 25 5.9 bit sequential buffer 26 6. interrupt functions 27 7. standby function 29 8. reset operation 30 9. instruction set 32 10. electrical specifications 40 11. characteristic curves (for reference only) 54 12. package drawings 60 13. recommended soldering conditions 62 appendix a. development tools 64 appendix b. related documents 65 5 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 1. pin configuration (top view) ? 42-pin plastic shrink dip v ss p40 p41 p42 p43 p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 p03/si/sb1 p10/int0 p11/int1 p12/int2 p13/ ti0 p20/pto0 p21 p22/pcl p23/buz xt1 xt2 reset x1 x2 p33 p32 p31 p30 av ss an7/kr3/p63 an6/kr2/p62 an5/kr1/p61 an4/kr0/p60 an3/p113 an2/p112 an1/p111 an0/p110 av ref ic v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 m pd75064cu- pd75066cu- pd75068cu- m m ? 44-pin plastic qfp ic : internally connected (this pin should be directly connected to v dd ) p112/an2 p113/an3 p60/kr0/an4 p61/kr1/an5 p62/kr2/an6 p63/kr3/an7 av ss p30 p31 p32 p33 int2/p12 int1/p11 int0/p10 sb1/si/p03 sb0/so/p02 sck /p01 int4/p00 p53 p52 p51 p50 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 nc p43 p42 p41 p40 v ss xt1 xt2 reset x1 x2 p13/ ti0 p20/pto0 p21 p22/pcl p23/buz v dd ic av ref p110/an0 p111/an1 nc 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 m pd75064gb- -3b4 pd75066gb- -3b4 pd75068gb- -3b4 m m 6 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) pin identifications p00 - 03 : port 0 p10 - 13 : port 1 p20 - 23 : port 2 p30 - 33 : port 3 p40 - 43 : port 4 p50 - 53 : port 5 p60 - 63 : port 6 p110 - 113 : port 11 kr0 - 3 : key return sck : serial clock si : serial input so : serial output sb0, 1 : serial bus 0, 1 reset : reset input ti0 : timer input 0 pto0 : programmable timer output 0 buz : buzzer clock pcl : programmable clock int0, 1, 4 : external vectored interrupt 0, 1, 4 int2 : external test input 2 x1, 2 : main system clock oscillation 1, 2 xt1, 2 : subsystem clock oscillation 1, 2 an0 - 7 : analog input 0 - 7 av ref : analog reference av ss : analog v ss v dd : positive power supply v ss : ground 7 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 2. block diagram basic interval timer timer/ counter #0 serial interface interrupt control watch timer a/d converter intbt intt0 intcsi intw ti0/p13 pto0/p20 si/sb1/p03 so/sb0/p02 sck/p01 int0/p10 int1/p11 int2/p12 int4/p00 buz/p23 av ref av ss alu rom program memory 4096 8 bits ( pd75064) 6016 8 bits ( pd75066) 8064 8 bits ( pd75068) decode and control program counter cy sp bank general register ram data memory 512 4 bits bit seq. buffer port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 11 p00 - p03 p10 - p13 p20 - p23 p30 - p33 p40 - p43 p50 - p53 p60 - p63 p110 - p113 clock output control clock divider clock generator sub main stand by control f x /2 n cpu clock f reset v ss v dd pcl/p22 xt1 xt2 x1 x2 kr0 - kr3 / p60 - p63 4 8 m m m 4 4 4 4 4 4 4 4 note an0 - an3 / p110 - p113 an4 - an7 / p60 - p63 note the m pd75064 uses the program counter of a 12-bit configuration, the m pd75066 and m pd75068 use that of a 13-bit configuration. 8 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) pin name p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 note 2 p31 note 2 p32 note 2 p33 note 2 p40 - p43 note 2 p50 - p53 note 2 p60 p61 p62 p63 p110 p111 p112 p113 i/o circuit type note 1 -a -b -c -c e-b e-b m m -d y-a input/ output input i/o i/o i/o input i/o i/o i/o i/o i/o input when reset input input input input high level (when pull- up resistors are provided) or high impedance high level (when pull- up resistors are provided) or high impedance input input 8-bit i/o function 4-bit input port (port0). for p01 to p03, pull-up resistors can be provided by software in units of 3 bits. with noise elimination function 4-bit input port (port1). pull-up resistors can be provided by soft- ware in units of 4 bits. 4-bit i/o port (port2). pull-up resistors can be provided by soft- ware in units of 4 bits. programmable 4-bit i/o port (port3). i/o can be specified bit by bit. pull-up resistors can be provided by software in units of 4 bits. n-ch open-drain 4-bit i/o port (port4). a pull-up resistor can be provided for each bit (mask option). breakdown volt- age is 10 v in open-drain mode. n-ch open-drain 4-bit i/o port (port5). a pull-up resistor can be provided for each bit (mask option). breakdown volt- age is 10 v in open-drain mode. programmable 4-bit i/o port (port6). i/o can be specified bit by bit. pull-up resistors can be provided by software in units of 4 bits. 4-bit input port (port11). notes 1. the circle ( ) indicates the schmitt trigger input. 2. can directly drive leds. b f f m b y 3. pin functions 3.1 port pins shared with int4 sck so/sb0 si/sb1 int0 int1 int2 ti0 pto0 pcl buz kr0/an4 kr1/an5 kr2/an6 kr3/an7 an0 an1 an2 an3 9 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) pin name ti0 pto0 pcl buz sck so/sb0 si/sb1 int4 int0 int1 int2 kr0 - kr3 an0 - an3 an4 - an7 av ref av ss x1, x2 xt1, xt2 reset ic v dd v ss i/o circuit type note 1 -c e-b e-b e-b -a -b -c -c -c -d y-a -d z z e e e e e shared with p13 p20 p22 p23 p01 p02 p03 p00 p10 p11 p12 p60 - p63/ an4 - an7 p110 - p113 p60 - p63/ kr0 - kr3 e e e e e e e e when reset e input input input input input input e e e input input e e e e e e e e input/ output input i/o i/o i/o i/o i/o i/o input input input i/o input i/o input e input input input e e e function input for receiving external event pulse signal for timer/event counter timer/event counter output clock output output frequency selectable (for buzzer output or system clock trimming) serial clock i/o serial data output serial bus i/o serial data input serial bus i/o edge-detective vectored interrupt input (both rising and falling edges enabled) edge-detective vectored interrupt input (detection edge selectable) edge-detective testable input (rising edge detection) parallel falling edge detection testable input for a /d converter only crystal/ceramic connection for main system clock generation. when external clock signal is used, the signal should be applied to x1, and its reverse phase signal to x2. crystal connection for subsystem clock genera- tion. when external clock signal is used, the signal should be applied to xt1, and its reverse phase signal to xt2. xt1 can be used as a 1-bit input (test). system reset input internally connected. (connect this pin directly to v dd ) positive power supply gnd potential 3.2 non-port pins 8-bit analog input reference voltage input gnd potential b f f m b b b y y b note 2 note 3 note 3 notes 1. the circle ( ) indicates the schmitt trigger input. 2. clock synchronous 3. asynchronous 10 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 3.3 pin input/output circuits the input/output circuit of each m pd75068 pin is shown below in a simplified manner. type a (for type e-b) cmos input buffer schmitt trigger input with hysteresis push-pull output which can be set to high impedance output (off for both p-ch and n-ch) p.u.r.: pull-up resistor p.u.r.: pull-up resistor type b type e-b type b-c type d (for type e-b, f-a) v dd in p-ch n-ch in in p-ch p.u.r. enable p.u.r. v dd v dd p-ch n-ch out data output disable p.u.r. v dd p.u.r. enable p-ch in/out data output disable type d type a (1/3) 11 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) type f-b type f-a type m type y (for type y-a , y-d) type m-c type y-a p.u.r.: pull-up resistor p.u.r.: pull-up resistor p.u.r.: pull-up resistor p.u.r.: pull-up resistor p.u.r. v dd p.u.r. enable p-ch in/out data output disable type d type b v dd p-ch n-ch in/out v dd p-ch p.u.r. p.u.r. enable output disable (p) data output disable output disable (n) n-ch (can withstand +10 v) in/out data v dd output disable p.u.r. enable (mask option) middle-voltage input buffer (can withstand +10 v) n-ch p.u.r. data output disable p.u.r. enable v dd p-ch in/out v dd v dd p-ch av ss n-ch sampl- ing c av ss reference voltage (from voltage tap of serial resistor string) input enable in in input buffer in instruction + ? (2/3) type y type a 12 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) type y-d p.u.r.: pull-up resistor type z p.u.r. v dd p.u.r. enable p-ch in/out data output disable type d type y type b av ref reference voltage av ss (3/3) 3.4 mask option selection the following mask options are available for selection for each pin. pin name p40 - p43, p50 - p53 xt1, xt2 1 pull-up resistor enabled (specifiable bit by bit) 1 feedback resistor enabled (if a subsystem clock is used) 2 pull-up resistor disabled (specifiable bit by bit) 2 feedback resistor disabled (if a subsystem clock is not used) mask option 13 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 3.5 handling unused pins table 3-1. handling unused pins pin recommended connection p00/int4 connect to v ss . p01/sck connect to v ss or v dd . p02/so/sb0 p03/si/sb1 p10/int0-p12/int2 connect to v ss . p13/ti0 p20/pto0 input state: connect to v ss or v dd . p21 output state: open p22/pcl p23/buz p30-p33 p40-p43 p50-53 p60/kr0/an4-p63/kr3/an7 p110/an0-p113/an3 connect to v ss or v dd . av ref connect to v ss . av ss xt1 connect to v ss or v dd . xt2 open ic directly connect to v dd . 14 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 4. memory configuration program memory (rom) ..... 4096 8 bits (0000h to 0fffh) : m pd75064 ..... 6016 8 bits (0000h to 177fh) : m pd75066 ..... 8064 8 bits (0000h to 1f7fh) : m pd75068 0000h to 0001h : vector table in which the program start address by reset is stored 0002h to 000bh : vector table in which the program start address by interrupt is stored 0020h to 007fh : table area to be referenced by geti instruction data memory data area ..... 512 4 bits (000h to 1ffh) peripheral hardware area ..... 128 4 bits (f80h to fffh) figure 4-1. program memory map (a) m pd75064 mbe 0 0 765 0000h address mbe 0 0 0002h mbe 0 0 0004h mbe 0 0 0006h mbe 0 0 0008h mbe 0 0 000ah 007fh 0080h 0020h 07ffh 0800h 0fffh 0 internal reset start address (high-order 4 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 4 bits) intbt/int4 start address (low-order 8 bits) int0 start address (high-order 4 bits) int0 start address (low-order 8 bits) int1 start address (high-order 4 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 4 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 4 bits) intt0 start address (low-order 8 bits) geti instruction reference table call ! addr instruction subroutine entry address br $addr instruction relative branch address (?5 to ?, +2 to +16) callf ! faddr instruction entry address brcb ! caddr instruction branch address branch destination address specified by geti instruction, subroutine entry address 0 0 0 0 0 0 4 15 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) (b) m pd75066 mbe 0 0 765 0000h address mbe 0 0 0002h mbe 0 0 0004h mbe 0 0 0006h mbe 0 0 0008h mbe 0 0 000ah 007fh 0080h 0020h 07ffh 0800h 0fffh 1000h 177fh 0 internal reset start address (high-order 5 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 5 bits) intbt/int4 start address (low-order 8 bits) int0 start address (high-order 5 bits) int0 start address (low-order 8 bits) int1 start address (high-order 5 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 5 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 5 bits) intt0 start address (low-order 8 bits) geti instruction reference table call ! addr instruction subroutine entry address br ! addr instruction brach address br $addr instruction relative branch address (?5 to ?, +2 to +16) callf ! faddr instruction entry address brcb ! caddr instruction branch address brcb ! caddr instruction branch address branch destination address specified by geti instruction, subroutine entry address 16 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) (c) m pd75068 mbe 0 0 765 0000h address mbe 0 0 0002h mbe 0 0 0004h mbe 0 0 0006h mbe 0 0 0008h mbe 0 0 000ah 007fh 0080h 0020h 07ffh 0800h 0fffh 1000h 1f7fh 0 internal reset start address (high-order 5 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 5 bits) intbt/int4 start address (low-order 8 bits) int0 start address (high-order 5 bits) int0 start address (low-order 8 bits) int1 start address (high-order 5 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 5 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 5 bits) intt0 start address (low-order 8 bits) geti instruction reference table call ! addr instruction subroutine entry address br ! addr instruction brach address br $addr instruction relative branch address (?5 to ?, +2 to +16) callf ! faddr instruction entry address brcb ! caddr instruction branch address brcb ! caddr instruction branch address branch destination address specified by geti instruction, subroutine entry address 17 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) figure 4-2. data memory map (8 4) data memory 000h 007h 008h 0ffh 100h 1ffh f80h fffh 256 4 256 4 128 4 bank 0 bank 1 bank 15 stack area general register area static ram (512 4) peripheral hardware area not contained 18 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 5. peripheral hardware functions 5.1 ports the following three types of i/o port are provided: ? cmos input ports (port0, 1, 11) : 12 ? cmos input/output ports (port2, 3, 6) : 12 ? n-ch open-drain input/output ports (port4, 5) : 8 total 32 table 5-1. functions of port note can directly drive leds. port (symbol) port0 port1 port3 note port6 port2 port4 note port5 note port11 function 4-bit input 4-bit i/o 4-bit i/o (n-ch open-drain, can withstand 10 v) 4-bit input operation/features can be read or tested regard- less of the operation mode of the dual function pin. can be specified for input/ output in bit units. can be specified for input/ output in 4-bit units. can be specified for input/ output in 4-bit units. ports 4 and 5 can be paired to input/output data in 8-bit units. 4-bit port dedicated to input remarks shared with the so/sb0, si/sb1, sck, int0-2, 4, and ti0 pins. port 6 is shared with pins kr0 to kr3 and pins an4 to an7. port 2 is shared with pto0, pcl, and buz pins. whether or not the internal pull-up resistor is provided can be specified for each bit by mask option. port 11 is shared with pins an0 to an3. 19 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) subsystem clock generator main system clock generator watch timer ?basic interval timer (bt) ?timer/event counter ?serial interface ?watch timer ?a /d converter (successive approximation type) ?int0 noise eliminator ?clock output circuit ? ? ? ? ? ? ? 1/2 to 1/4096 frequency divider selec- tor selec- tor frequency divider ?cpu ?int0 noise eliminator ?clock output circuit f oscillator disable signal internal bus halt note stop note pcc2, pcc3 clear signal wait release signal from bt standby release signal from interrupt control circuit reset signal xt1 xt2 x1 x2 4 wm.3 scc scc3 scc0 pcc pcc0 pcc1 pcc2 pcc3 stop f/f q s r halt f/f s q r f xt f x 1/2 1/16 1/4 ? ? ? 5.2 clock generator the clock generator operates according to the statuses of the processor clock control register (pcc) and the system clock control register (scc). two types of clock are provided: main system clock and subsystem clock, and the instruction execution time can be changed. ? 0.95 m s / 1.91 m s / 15.3 m s (operated with main system clock at 4.19 mhz) ? 122 m s (operated with subsystem clock at 32.768 khz) figure 5-1. clock generator block diagram note instruction execution remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. f = cpu clock 4. pcc: processor clock control register 5. scc: system clock control register 6. one clock cycle (t cy ) at f is equal to one machine cycle of an instruction. for t cy , refer to ac characteristics in 10. electrical specifications . 20 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 5.3 clock output circuit the clock output circuit outputs clock pulses from the p22/pcl pin, and is used to supply clock pulses to remote unit controller and peripheral lsis. ? clock output (pcl): f , 524 khz, 262 khz, 65.5 khz (f x = at 4.19 mhz) figure 5-2. clock output circuit configuration remark measures are taken to prevent outputting a narrow pulse when selecting clock output enable/disable. from the clock generator clom3 0 clom1 clom0 clom selector output buffer port 2 input/ output mode specification bit p22 output latch p22/pcl internal bus 4 f f x / 2 3 f x / 2 4 f x / 2 6 port2.2 bit 2 of pmgb 21 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 5.4 basic interval timer the basic interval timer has these functions: ? interval timer operation which generates a reference timer interrupt ? watchdog timer application which detects a program runaway ? selection of wait time for releasing the standby mode and counting the wait time ? reading out the count value figure 5-3. basic interval timer configuration note instruction execution from the clock generator internal bus 4 f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx basic interval timer (8-bit frequency divider circuit) clear signal clear signal bt interrupt request flag vectored interrupt request signal irqbt wait release signal for standby release set signal bt 8 btm3 btm2 btm1 btm0 btm set1 note 3 22 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 5.5 watch timer the m pd75068 has an on-chip 1-ch watch timer. the watch timer has the following functions: ? sets the test flag (irqw) with a 0.5-sec interval. the standby mode can be released by irqw. ? the 0.5-second interval can be generated from either the main system clock or subsystem clock. ? the time interval can be made 128 times faster (3.91 ms) by selecting the fast mode. this is convenient for program debugging, testing, etc. ? any of the frequencies 2.048 khz, 4.096 khz, and 32.768 khz can be output to the p23/buz pin. this can be used for beep and system clock frequency trimming. ? the frequency divider circuit can be cleared so that a zero-second start of the watch can be made. figure 5-4. watch timer block diagram remark ( ) is for f x = 4.194304 mhz, f xt = 32.768 khz. p23/buz internal bus 8 selector from the clock generator f x 128 (32.768 khz) f xt (32.768 khz) ? ? ? selector frequency divider selector intw irqw set signal 2 hz 0.5 sec wm7 0 wm5 wm4 wm3 wm2 wm1 wm0 p23 output latch bit 2 of pmgb port2.3 output buffer clear signal f w (32.768 khz) bit test instruction port 2 input/ output mode wm (4 khz) (2 khz) f w 2 7 (256 hz: 3.91 ms) f w 2 14 f w 2 3 f w 2 4 23 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 5.6 timer/event counter the m pd75068 has an on-chip 1-ch timer/event counter. the timer/event counter has the following functions: ? programmable interval timer operation ? outputs square-wave signal of a user-selectable frequency to the pto0 pin ? event counter operation ? divides the ti0 pin input by n and outputs to the pto0 pin (frequency divider operation) ? supplies serial shift clock to the serial interface circuit ? count condition read-out function. figure 5-5. block diagram of timer / event counter count register (8) p13/ ti0 note instruction execution mpx timer operation start signal ? ? ? 8 8 8 from the clock generator internal bus tm07 tm06 tm05 tm04 tm03 tm02 tm01 tm00 port1.3 (refer to fig. 5-1.) comparator (8) modulo register (8) to enable flag p20 output latch signal port 2 input/ output mode clear signal t0 tmod0 bit 2 of pgmb p20/pto0 output buffer reset reset irqt0 clear signal tout f/f tm0 set1 note input buffer irqt0 set signal intt0 port2.0 toe0 to serial interface cp match 8 8 24 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 5.7 serial interface (1) serial interface function the m pd75068 contains a clock synchronous 8-bit serial interface, which has four modes. ? operation halt mode ? 3-wire serial i/o mode ? 2-wire serial i/o mode ? sbi (serial bus interface mode) figure 5-6. block diagram of serial interface internal bus 8 8 8 8/4 p03/si/sb1 p02/so/sb0 p01/sck (8) f x /2 3 f x /2 4 f x /2 6 tout f/f (from timer/ event counter) csim reld cmdd ackd ackt acke bsye relt cmdt dq set clr (8) (8) sbic bit test slave address register (sva) address comparator shift register (sio) match signal bit manipulation so latch bit test selector busy/ acknowledge output circuit bus release/ command/ acknowledge detection circuit serial clock counter serial clock control circuit intcsi control circuit irqcsi set signal intcsi p01 output latch serial clock selector external sck selector 25 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 5.8 a/d converter the m pd75068 contains an 8-bit analog/digital (a / d) converter that has eight analog input channels (an0 - an7). the a /d converter employs the successive-approximation method. figure 5-7. block diagram of a/d converter internal bus 8 + ? an0/p110 an1/p111 an2/p112 an3/p113 an4/kr0/p60 an5/kr1/p61 an6/kr2/p62 an7/kr3/p63 av ref av ss r 8 r r/2 r/2 8 adm 0 adm1 eoc soc adm4 adm5 adm6 0 control circuit multi- plexer sample and hold circuit comparator sa register (8) tap decoder series resistor string r 26 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 5.9 bit sequential buffer: 16 bits the bit sequential buffer is a data memory specifically provided for bit manipulation. with this buffer, addresses and bit specifications can be sequentially updated by bit manipulation operation. therefore, this buffer is very useful for processing long data in bit units. figure 5-8. bit sequential buffer format 3210321032103210 bsb3 bsb2 bsb1 bsb0 fc3h fc2h fc1h fc0h l = f l = c l = b l = 8 l = 7 l = 4 l = 3 l = 0 decs l incs l address bit l register symbol remark for "pmem.@l" addressing, the specification bit is shifted according to the l register. 27 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 6. interrupt functions the m pd75068 has six different interrupt sources. in addition, multiple interrupts with priority control are possible. two types of test sources are provided. of these test sources, int2 has two types of edge detection testable inputs. table 6-1. interruption source types interruption vectored interrupt request signal interruption source in/out order note1 (vector table address) (reference time interval signal from basic interval timer) (detection of both rising edge and falling edge is valid.) out 2 vrq2 (0004h) out 3 vrq3 (0006h) (serial data transmission completion signal) (coincidence signal of programmable intt0 timer/counter count register and modulo in 5 vrq5 (000ah) register) (detection of rising edge of input to int2 note2 int2 pin or detection of falling edge of out any input to kr0 to kr3) intw note2 (signal from watch timer) in notes 1. the interruption order shows the priority order of the pins when several interruption requests occur at the same time. 2. test source. like the interruption source, it is influenced by the interruption enable flag. however, vectored interrupt will not occur. the interrupt control circuit of the m pd75068 has the following functions: ? hardware controlled vectored interrupt function which can control whether or not to acknowledge an interrupt based on the interrupt flag (ie ) and interrupt master enable flag (ime) ? the interrupt start address can be set arbitrarily. ? interrupt request flag (irq ) test function (an interrupt generation can be confirmed by software) ? standby mode release (interrupts to be released can be selected by the interrupt enable flag) in intbt int4 (selection of rising edge detection or falling edge detection) int0 int1 intcsi vrq1 (0002h) 1 test input signal (set irq and irqw) vrq4 (0008h) 4 in out 28 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) figure 6-1. block diagram of interrupt control circuit internal bus 3 1 irqbt irq4 irq0 irq1 irqcsi irqt0 irqw irq2 int4 /p00 int0 /p10 int1 /p11 note intcsi intt0 intw int2 /p12 an4/kr0/p60 an7/kr3/p63 vrqn ime ist0 im2 int bt interrupt enable flag (iexxx) both-edge detection circuit edge detection circuit rising edge detection circuit falling edge detection circuit selec- tor decoder priority control circuit vector table address generator standby release signal im0 im1 note noise eliminator edge detection circuit 29 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 7. standby function the m pd75068 has two different standby modes (stop mode and halt mode) to reduce power dissipation while waiting for program execution. table 7-1. standby mode statuses note a/d converter's operation in halt mode is possible only when the main system clock operates. instruction for setting system clock for setting clock oscillator basic interval timer serial interface timer/event counter watch timer a/d converter external interrupt cpu release signal halt mode halt instruction can be set either with the main system clock or the subsystem clock. only the cpu clock f stops its operation (oscillation continues). can operate only at main system clock oscillation (irqbt is set at reference time intervals.). can operate only when external sck input is selected as the serial clock or at main system clock oscillation. can operate only when ti0 pin input is specified as the count clock or at main system clock oscillation. can operate. can operate. note an interrupt request signal from hard- ware whose operation is enabled by the interrupt enable flag or the reset signal input stop mode stop instruction can be set only when operating on the main system clock. only the main system clock stops its operation. does not operate. can operate only when the external sck input is selected for the serial clock. can operate only when the ti0 pin input is selected for the count clock. can operate when f xt is selected as the count clock. does not operate. int1, int2, and int4 can operate. only int0 cannot operate. does not operate. an interrupt request signal from hard- ware whose operation is enabled by the interrupt enable flag or the reset signal input opera- tion status 30 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) reset input in standby mode contents of lower 4 bits of address 0000h in program memory are set to pc11 - 8, and that of 0001h are set to pc7 - 0. contents of lower 5 bits of address 0000h in program memory are set to pc12 - 8, and that of 0001h are set to pc7 - 0. retained 0 0 the contents of bit 7 of address 0000h of the program memory is set to mbe. undefined retained note retained 0 undefined 0 0 ffh 0 0, 0 0 counter (bt) mode register (btm) counter (t0) modulo register (tmod0) mode register (tm0) toe0, tout f/f mode register (wm) basic interval timer timer/event counter watch timer 8. reset operation when the reset signal is input, the m pd75068 is reset and all hardware is initialized as indicated in table 8-1. figure 8-1 shows the reset operation timing. figure 8-1. reset operation by reset input table 8-1. status of all hardware after reset (1/2) reset input during operation same operation as that in standby state same operation as that in standby state undefined 0 0 same operation as that in standby state undefined undefined undefined 0 undefined 0 0 ffh 0 0, 0 0 note data of address 0f8h to 0fdh of the data memory becomes undefined when the reset signal is input. hardware program counter (pc) m pd75064 m pd75066 m pd75068 psw carry flag (cy) skip flag (sk0-2) interrupt status flag (ist0) bank enable flag (mbe) stack pointer (sp) data memory (ram) general purpose register (x, a, h, l, d, e, b, c) bank selection register (mbs) reset input operation mode or standby mode halt mode operation mode internal reset operation wait (approx. 31.3 ms/4.19 mhz) 31 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) shift register (sio) operation mode register (csim) sbi control register (sbic) slave address register (sva) processor clock control register (pcc) system clock control register (scc) clock output mode register (clom) interrupt irq1, irq2, request flag and irq4 ( irqxxx ) other than above interrupt enable flag (ie ) interrupt master enable flag (ime) int0, 1, 2, mode register (im0, im1, im2) output buffer output latch input/output mode register (pmga, pmgb) pull-up resistor specification register (poga) mode register (adm) sa register (sa) reset input during operation undefined 0 0 undefined 0 0 0 undefined 0 0 0 0, 0, 0 off clear (0) 0 0 04h undefined undefined reset input in standby mode retained 0 0 retained 0 0 0 undefined 0 0 0 0, 0, 0 off clear (0) 0 0 04h undefined retained table 8-1. status of all hardware after reset (2/2) serial interface clock genera- tor, clock output circuit interrupt function digital port a/d converter hardware bit sequential buffer (bsb0-bsb3) 32 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 9. instruction set (1) operand identifier and its descriptive method the operands are described in the operand column of each instruction according to the descriptive method for the operand format of the appropriate instructions. details should be followed by " ra75x assembler package user's manual, language ." for descriptions in which alternatives exist, one element should be selected. capital letters and plus and minus signs are keywords; therefore, they should be described as they are. for immediate data, the appropriate numerical values or labels should be described. identifier reg reg1 rp rp1 rp2 rpa rpa1 n4 n8 mem note bit fmem pmem addr caddr faddr taddr portn iexxx mbn description x, a, b, c, d, e, h, l x, b, c, d, e, h, l xa, bc, de, hl bc, de, hl bc, de hl, de, dl de, dl 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label fb0h - fbfh, ff0h - fffh immediate data or label fc0h - fffh immediate data or label m pd75064 0000h - 0fffh immediate data or label m pd75066 0000h - 177fh immediate data or label m pd75068 0000h - 1f7fh immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20h - 7fh immediate data (however, bit 0 = 0) or label port0 - port6, port11 iebt, iecsi, iet0, ie0, ie1, ie2, ie4, iew mb0, mb1, mb15 note only even address can be specified for mem when processing 8-bit data. (2) symbol definitions in operation description a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : pair register (xa); 8-bit accumulator bc : pair register (bc) de : pair register (de) 33 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) hl : pair register (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag portn : port n (n = 0 to 6, 11) ime : interrupt master enable flag ie : interrupt enable flag mbs : memory bank selection register pcc : processor clock control register . : address bit delimiter ( ) : contents addressed by h : hexadecimal data (3) symbols used for the addressing area column remarks 1. mb indicates the memory bank that can be accessed. 2. for *2, mb = 0 regardless of mbe and mbs settings. 3. for *4 and *5, mb = 15 regardless of mbe and mbs. 4. for *6 to *10, each addressable area is indicated. mb = mbe mbs (mbs = 0, 1, 15) mb = 0 mbe = 0: mb = 0 (00h - 7fh) mb = 15 (80h - ffh) mbe = 1: mb = mbs (mbs = 0, 1, 15) mb = 15, fmem = fb0h - fbfh, ff0h - fffh mb = 15, pmem = fc0h - fffh pd75064 addr = 0000h - 0fffh pd75066 addr = 0000h - 177fh pd75068 addr = 0000h - 1f7fh addr = (current pc) e 15 to (current pc) e 1 (current pc) + 2 to (current pc) + 16 pd75064 caddr = 0000h - 0fffh pd75066 caddr = 0000h - 0fffh (pc 12 = 0) or pd75068 caddr = 0000h - 0fffh (pc 12 = 0) or = 1000h - 1f7fh (pc 12 = 1) faddr = 0000h - 07ffh taddr = 0020h - 007fh *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 data memory addressing program memory addressing m m m m m m = 1000h - 177fh (pc 12 = 1) 34 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) m pd75064, m pd75064(a) m pd75066, m pd75066(a) m pd75068, m pd75068(a) m pd75064 m pd75066 m pd75068 (4) description of machine cycle column s indicates the number of machine cycles necessary for skipping any skip instruction. the value of s changes as follows: ? when no skip is performed s = 0 ? when a 1-byte or 2-byte instruction is skipped s = 1 ? when a 3-byte instruction (br !addr note , call !addr instruction) is skipped s = 2 note br !addr instruction is not provided in the m pd75064. caution the geti instruction is skipped in one machine cycle. one machine cycle is equivalent to one cpu clock f cycle. therefore, the length of the machine cycle can be selected from three different lengths by the pcc setting. (5) representative products listed in operation column the products listed in the operation column ( m pd75064, 75066, 75068) stand for the products listed below. h 35 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) group transfer table reference arithme- tic mne- monic mov xch movt adds addc subs subc operand a, #n4 reg1, #n4 xa, #n8 hl, #n8 rp2, #n8 a, @hl a, @rpa1 xa, @hl @hl, a @hl, xa a, mem xa, mem mem, a mem, xa a, reg xa, rp reg1, a rp1, xa a, @hl a, @rpa1 xa, @hl a, mem xa, mem a, reg1 xa, rp xa, @pcde xa, @pcxa a, #n4 a, @hl a, @hl a, @hl a, @hl bytes 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 1 1 1 1 1 1 1 ma- chine cycle 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 3 3 1 + s 1 + s 1 1 + s 1 skip condition string a string a string b carry carry borrow address- ing area *1 *2 *1 *1 *1 *3 *3 *3 *3 *1 *2 *1 *3 *3 *1 *1 *1 *1 operation a ? n4 reg1 ? n4 xa ? n8 hl ? n8 rp2 ? n8 a ? (hl) a ? (rpa1) xa ? (hl) (hl) ? a (hl) ? xa a ? (mem) xa ? (mem) (mem) ? a (mem) ? xa a ? reg xa ? rp reg1 ? a rp1 ? xa a ? (hl) a ? (rpa1) xa ? (hl) a ? (mem) xa ? (mem) a ? reg1 xa ? rp ? m pd75064 xa ? (pc 11-8 + de) rom ? m pd75066, 75068 xa ? (pc 12-8 + de) rom ? m pd75064 xa ? (pc 11-8 + xa) rom ? m pd75066, 75068 xa ? (pc 12-8 + xa) rom a ? a + n4 a ? a + (hl) a, cy ? a + (hl) + cy a ? a C (hl) a, cy ? a C (hl) C cy 36 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) group arithmetic accumulator manipulation increment/ decrement compari- son carry flag manipu- lation memory bit manipu- lation mne- monic and or xor rorc not incs decs ske set1 clr1 skt not1 set1 clr1 skt skf sktclr operand a, #n4 a, @hl a, #n4 a, @hl a, #n4 a, @hl a a reg @hl mem reg reg, #n4 @hl, #n4 a, @hl a, reg cy cy cy cy mem.bit fmem.bit pmem. @l @h+mem.bit mem.bit fmem.bit pmem. @l @h+mem.bit mem.bit fmem.bit pmem. @l @h+mem.bit mem.bit fmem.bit pmem. @l @h+mem.bit fmem.bit pmem. @l @h+mem.bit bytes 2 1 2 1 2 1 1 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ma- chine cycle 2 1 2 1 2 1 1 2 1 + s 2 + s 2 + s 1 + s 2 + s 2 + s 1 + s 2 + s 1 1 1 + s 1 2 2 2 2 2 2 2 2 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s skip condition reg = 0 (hl) = 0 (mem) = 0 reg = fh reg = n4 (hl) = n4 a = (hl) a = reg cy = 1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@l) = 0 (@h + mem.bit) = 0 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 address- ing area *1 *1 *1 *1 *3 *1 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 operation a ? a n4 a ? a (hl) a ? a n4 a ? a (hl) a ? a n4 a ? a (hl) cy ? a 0 , a 3 ? cy, a nC1 ? a n a ? a reg ? reg + 1 (hl) ? (hl) + 1 (mem) ? (mem) + 1 reg ? reg C 1 skip if reg = n4 skip if (hl) = n4 skip if a = (hl) skip if a = reg cy ? 1 cy ? 0 skip if cy = 1 cy ? cy (mem.bit) ? 1 (fmem.bit) ? 1 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 1 (h + mem 3-0 .bit) ? 1 (mem.bit) ? 0 (fmem.bit) ? 0 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 0 (h + mem 3-0 .bit) ? 0 skip if (mem.bit) = 1 skip if (fmem.bit) = 1 skip if (pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 skip if (h + mem 3-0 .bit) = 1 skip if (mem.bit) = 0 skip if (fmem.bit) = 0 skip if (pmem 7-2 + l 3-2 .bit(l 1-0 )) = 0 skip if (h + mem 3-0 .bit) = 0 skip if (fmem.bit) = 1 and clear skip if (pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 and clear skip if (h + mem 3-0 .bit) = 1 and clear 37 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) mne- monic and1 or1 xor1 br brcb call operand cy, fmem.bit cy, pmem.@l cy, @h+mem.bit cy, fmem.bit cy, pmem.@l cy, @h+mem.bit cy, fmem.bit cy, pmem.@l cy, @h+mem.bit addr !addr note $addr !caddr !addr bytes 2 2 2 2 2 2 2 2 2 C 3 1 2 3 ma- chine cycle 2 2 2 2 2 2 2 2 2 C 3 2 2 3 skip condition address- ing area *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 *6 *7 *8 *6 operation cy ? cy (fmem.bit) cy ? cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy ? cy (h + mem 3-0 .bit) cy ? cy (fmem.bit) cy ? cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy ? cy (h + mem 3-0 .bit) cy ? cy (fmem.bit) cy ? cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy ? cy (h + mem 3-0 .bit) ? m pd75064 pc 11-0 ? addr (appropriate instructions are selected from brcb !caddr, and br $addr by the assembler.) ? m pd75066, 75068 pc 12-0 ? addr (appropriate instructions are selected from br !addr, brcb !caddr, and br $addr by the assembler.) ? m pd75066, 75068 pc 12-0 ? addr ? m pd75064 pc 11-0 ? addr ? m pd75066, 75068 pc 12-0 ? addr ? m pd75064 pc 11-0 ? caddr 11-0 ? m pd75066, 75068 pc 12-0 ? pc 12 + caddr 11-0 ? m pd75064 (sp C 4)(sp C 1)(sp C 2) ? pc 11-0 (sp C 3) ? mbe, 0, 0, 0 pc 11-0 ? addr, sp ? sp C 4 ? m pd75066, 75068 (sp C 4)(sp C 1)(sp C 2) ? pc 11-0 (spC3) ? mbe, 0, 0, pc 12 pc 12-0 ? addr, sp ? sp C 4 note br !addr instruction is not provided in the m pd75064. group memory bit mani- pulation branch sub- routine stack control 38 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) group sub- routine stack control mne- monic callf ret rets reti push pop operand !faddr rp bs rp bs bytes 2 1 1 1 1 2 1 2 ma- chine cycle 2 3 3 + s 3 1 2 1 2 skip condition un- condi- tional address- ing area *9 operation ? m pd75064 (sp C 4)(sp C 1)(sp C 2) ? pc 11-0 (spC3) ? mbe, 0, 0, 0 pc 11-0 ? 00, faddr, sp ? sp C 4 ? m pd75066, 75068 (sp C 4)(sp C 1)(sp C 2) ? pc 11-0 (spC3) ? mbe, 0, 0, pc 12 pc 12-0 ? 00, faddr, sp ? sp C 4 ? m pd75064 mbe, 0, 0, 0 ? (sp + 1) pc 11-0 ? (sp)(sp + 3)(sp + 2) sp ? sp + 4 ? m pd75066, 75068 mbe, 0, 0, pc 12 ? (sp + 1) pc 11-0 ? (sp)(sp + 3)(sp + 2) sp ? sp + 4 ? m pd75064 mbe, 0, 0, 0 ? (sp + 1) pc 11-0 ? (sp)(sp + 3)(sp + 2) sp ? sp + 4, then skip unconditionally ? m pd75066, 75068 mbe, 0, 0, pc 12 ? (sp + 1) pc 11-0 ? (sp)(sp + 3)(sp + 2) sp ? sp + 4, then skip unconditionally ? m pd75064 mbe, 0, 0, 0 ? (sp + 1) pc 11-0 ? (sp)(sp + 3)(sp + 2) psw ? (sp + 4)(sp + 5), sp ? sp + 6 ? m pd75066, 75068 mbe, 0, 0, pc 12 ? (sp + 1) pc 11-0 ? (sp)(sp + 3)(sp + 2) psw ? (sp + 4)(sp + 5), sp ? sp + 6 (sp C 1)(sp C 2) ? rp, sp ? sp C 2 (sp C 1) ? mbs, (sp C 2) ? 0, sp ? sp C 2 rp ? (sp + 1)(sp), sp ? sp + 2 mbs ? (sp + 1), sp ? sp + 2 39 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) group interrupt control input/ output cpu control special mne- monic ei di in out halt stop nop sel geti operand iexxx iexxx a, portn xa, portn portn, a portn, xa mbn taddr bytes 2 2 2 2 2 2 2 2 2 2 1 2 1 ma- chine cycle 2 2 2 2 2 2 2 2 2 2 1 2 3 address- ing area *10 operation ime ? 1 iexxx ? 1 ime ? 0 iexxx ? 0 a ? portn (n = 0 - 6, 11) xa ? portn +1 ,portn (n = 4, 6) portn ? a (n = 2 - 6) portn +1 , portn ? xa (n = 4, 6) set halt mode (pcc.2 ? 1) set stop mode (pcc.3 ? 1) no operation mbs ? n (n = 0, 1, 15) ? m pd75064 ? for the tbr instruction pc 11-0 ? (taddr) 3-0 + (taddr + 1) ? for the tcall instruction (sp C 4)(sp C 1)(sp C 2) ? pc 11-0 (sp C 3) ? mbe, 0, 0, 0 pc 11-0 ? (taddr) 3-0 + (taddr + 1) sp ? sp C 4 ? for other than the tbr and tcall instruction (taddr) (taddr + 1) is executed. ? m pd75066, 75068 ? for the tbr instruction pc 12-0 ? (taddr) 4-0 + (taddr + 1) ? for the tcall instruction (sp C 4)(sp C 1)(sp C 2) ? pc 11-0 (sp C 3) ? mbe, 0, 0, pc 12 pc 12-0 ? (taddr) 4-0 + (taddr + 1) sp ? sp C 4 ? for other than the tbr and tcall instruction (taddr) (taddr + 1) is executed. ---------------------------------------------- ---------------------------------------------- ----------------- ----------------- ---------------------------------------------- ---------------------------------------------- ----------------- ----------------- skip condition depends on the refer- ence instruction. depends on the refer- ence instruction. caution when executing the in/out instruction, mbe must be set to 0, or mbe and mbs must be set to 1 and 15, respectively. 40 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 10. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit power supply voltage except ports 4 and 5 C0.3 to v dd +0.3 v input voltage on-chip pull-up resistor C0.3 to v dd +0.3 v ports 4 and 5 n-ch openCdrain C0.3 to +11 v output voltage C0.3 to v dd +0.3 v high level output per pin C10 ma current all output pins C30 ma low level output peak value 30 ma current one pin of ports 0, 3, 4, and 5 rms value 15 ma peak value 20 ma one pin of ports 2 and 6 rms value 5 ma peak value 160 ma total of ports 0, 3, 4 and 5 rms value 120 ma peak value 30 ma total of ports 2 and 6 rms value 20 ma operating ambient temperature storage temperature note rms value is calculated using the following expression: [rms value] = [peak value] ? duty ratio caution if any of the items exceeds the absolute maximum ratings, even momentarily, this may damage product quality. the absolute maximum ratings are values that may physically damage products. be sure to use the products within the ratings. v dd v i1 v i2 v o i oh i ol note t opt t stg C65 to +150 c C40 to +85 c C0.3 to +7.0 v 41 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) recommended resonator parameter conditions min. typ. max. unit constant v dd = oscilla- tion voltage 1.0 5.0 note3 mhz range oscillation stabilization time note2 oscillation frequency (f x ) note1 v dd = 4.5 to 6.0 v oscillation stabilization time note2 30 ms x1 input frequency (f x ) note1 x1 input high-/low-level 100 500 ns width (t xh , t xl ) 4ms 1.0 5.0 note3 mhz notes 1. the oscillation frequency indicates characteristics of the oscillator only. for the instruction execution time, refer to the ac characteristics. 2. the oscillation stabilization time is the required time for oscillation to stabilize after the voltage level of v dd reaches the min. value of the oscillation voltage range or releasing the stop mode. 3. when the oscillation frequency is 4.19 mhz < f x 5.0 mhz, selection of pcc = 0011 with 1 machine cycle of less than 0.95 m s for instruction execution time is not possible. caution if the main system clock oscillator is used, the wiring in the area indicated with broken lines in the recommended constant illustration should be routed observing the points described below to avoid influence of wiring capacitance, etc. ? route as short as possible. ? do not cross the wires. ? route the wires away from lines where changing high current flows. ? make the connecting point of the capacitors in the oscillation circuit to have always the same potential as v ss . do not route the connecting point to another ground pattern on the board where high current flows. ? do not use the oscillator as a signal source of other circuits. ceramic resonator crystal resonator external clock x1 x2 c2 c1 v ss x1 x2 c2 c1 v ss 10 ms 1.0 4.19 5.0 note3 mhz x1 x2 pd74hcu04 m oscillation frequency (f x ) note1 42 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) recommended min. typ. max. unit resonator parameter conditions constant oscillation frequency (f xt ) note1 v dd = 4.5 to 6.0 v oscillation stabilization time note2 xt1 input 32 100 khz frequency (f xt ) note1 xt1 input high-/ low-level width (t xth ,t xtl ) notes 1. the oscillation frequency indicates characteristics of the oscillator only. for the instruction execution time, refer to the ac characteristics. 2. the oscillation stabilization time is the required time for oscillation to stabilize after the voltage level of v dd reaches the min. value of the oscillation voltage range. caution if the subsystem clock oscillator is used, the wiring in the area indicated with broken lines in the recommended constant illustration should be routed observing the points described below to avoid influence of wiring capacitance, etc. ? route as short as possible. ? do not cross the wires. ? route the wires away from lines where changing high current flows. ? make the connecting point of the capacitors in the oscillation circuit to have always the same potential as v ss . do not route the connecting point to another ground pattern on the board where high current flows. ? do not use the oscillator as a signal source of other circuits. especially when using the subsystem clock, be sure to design wiring so as to minimize noise. the subsystem clock oscillator uses a low-amplification circuit to minimize power dissipation. as a result, malfunctions due to noise are more liable to occur than with the main system clock oscillator. 32 32.768 50 khz 1.0 2 s 10 s 515 m s crystal resonator external clock xt1 xt2 c4 c3 v ss r xt1 xt2 43 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) recommended oscillator constant main system clock: ceramic (t a = C40 to +85 c) frequency (mhz) kbr-2.0 ms pbrc 2.00a kbr-4.19 msa pbrc 4.19a kbr-4.19 mks kbr-4.19 mws csb1000j note 1.00 100 100 2.7 rd = 5.6 k w csa2.0mg040 100 100 2.8 cst2.0mgw093 2.00 internal internal csac2.0mgcme 15 15 chip product csa4.19mgu 30 30 cst4.19mguw internal internal note when the murata's csb1000j ceramic resonator (1.00 mhz) is used, the limiting resistor (rd = 5.6 k w ) is required (see figure below). when using other recommended resonators, the limiting resistor is not required. example of recommended main system clock circuit (when using csb1000j of murata) main system clock: xtal frequency (mhz) 2.00 2.8 daisinku hc-49/u 4.19 8 8 6.0 (t a = C40 to +85 c) 5.00 2.00 3.1 4.19 3.2 manufacturer c1 (pf) c2 (pf) part number min. (v) max. (v) remarks 6.0 6.0 2.00 47 47 2.5 4.19 33 33 4.19 2.7 kyocera murata manufacturing 2.7 oscillation voltage range recommended circuit constant part number manufacturer min. (v) max. (v) remarks 2.7 c1 (pf) c2 (pf) kinseki hc-49/u 22 22 6.0 (t a = C20 to +70 c) recommended circuit constant oscillation voltage range x1 x2 rd c2 c1 csb1000j 4.19 internal internal 44 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol conditions min. typ. max. unit high-level input v ih1 ports 2, 3, and 11 0.7 v dd v dd v voltage v ih2 ports 0,1,6, reset 0.8 v dd v dd v on-chip pull-up resistor 0.7 v dd v dd v v ih3 ports 4 and 5 n-ch open-drain 0.7 v dd 10 v v ih4 x1, x2, xt1, xt2 v dd C0.5 v dd v low-level input v il1 ports 2 through 5 and 11 0 0.3 v dd v voltage v il2 ports 0, 1, 6, reset 0 0.2 v dd v v il3 x1, x2, xt1, xt2 0 0.4 v high-level output v dd = 4.5 to 6.0 v , i oh = C1 ma v dd C1.0 v voltage i oh = C100 m av dd C0.5 v low-level output v ol ports 4 and 5 v dd = 4.5 to 6.0 v 0.7 2.0 v i ol = 15 ma port 3 v dd = 4.5 to 6.0 v 0.3 2.0 v i ol = 15 ma v dd = 4.5 to 6.0 v , i ol = 1.6 ma 0.4 v i ol = 400 m a 0.5 v sb0, sb1 n-ch open-drain 0.2 v dd v pull-up resistor 3 1 k w high-level input i lih1 other than pins below 3 m a leakage current v i = v dd i lih2 x1, x2, xt1, xt2 20 m a ports 4 and 5 (n-ch open-drain) low-level input i lil1 other than pins below C3 m a leakage current v i = 0 v i lil2 x1, x2, xt1, xt2 C20 m a high-level output i loh1 v o = v dd 3 m a leakage current ports 4 and 5 (n-ch open-drain) low-level output i lol v o = 0 v C3 m a leakage current on-chip pull-up p01, 02, 03, v dd = 5.0 v 10 % 15 40 80 k w resistor r u1 ports 1, 2, 3 and 6 v i = 0 v v dd = 3.0 v 10 % 30 300 k w ports 4 and 5 v dd = 5.0 v 10 % 15 40 70 k w r u2 v o = v dd C 2.0 v v dd = 3.0 v 10 % 10 60 k w v oh voltage i lih3 v i = 10 v 20 m a i loh2 v o = 10 v 20 m a (cont.) 45 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) i dd4 515 m a parameter symbol conditions min. typ. max. unit supply current note1 v dd = 5.0 v 10 % note 3 2.0 6.0 ma i ddi 4.19 mhz note 2 v dd = 3.0 v 10 % note 4 0.2 0.6 ma crystal oscillation c1 = c2 = 22 pf halt v dd = 5.0 v 10 % 400 1200 m a i dd2 mode v dd = 3.0 v 10 % 120 400 m a i dd3 v dd = 3.0 v 10 % 10 30 m a 32.768 khz note 5 crystal oscillation halt v dd = 3.0 v 10 % mode v dd = 5.0 v 10 % 0.5 20 m a i dd5 0.1 10 m a t a = 25 c 0.1 5 m a notes 1. current which flows in the on-chip pull-up resistor is not included. 2. including oscillation of the subsystem clock. 3. when the processor clock control register (pcc) is set to 0011 and the device is operated in the high- speed mode. 4. when pcc is set to 0000 and the device is operated in the low-speed mode. 5. when the system clock control register (scc) is set to 1001 and the device is operated on the sub- system clock, with main system clock oscillation stopped. dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) v dd = 3.0 v 10 % xt1 = 0 v stop mode 46 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) ac characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol conditions min. typ. max. unit cpu clock operating on main v dd = 4.5 to 6.0 v 0.95 64 m s cycle time note 1 system clock ( minimum 3.8 64 m s instruction execution time = operating on subsystem clock 114 122 125 m s 1 machine cycle ) ti0 input v dd = 4.5 to 6.0 v 0 1 mhz frequency f ti 0 275 khz ti0 input high and v dd = 4.5 to 6.0 v 0.48 m s low level width 1.8 m s interrupt input high int0 note2 m s and low level width int1, int2, int4 10 m s kr0 to kr3 10 m s reset low level t rsl 10 m s width capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 15 pf unmeasured pins returned to 0 v. output capacitance c o 15 pf i/o capacitance c io 15 pf t cy t tih , t til t inth , t intl t cy vs v dd (operating on main system clock) cycle time t cy [ s] supply voltage v dd [v] 0 1 2 3 4 5 6 0.5 1 2 3 4 5 60 64 70 6 operation guarantee range m notes 1. the cycle time (minimum instruction execution time) of the cpu clock ( f ) is determined by the oscillation frequency of the connected resonator, the system clock control register (scc), and the processor clock control register (pcc). the figure at the right indicates the cycle time t cy versus supply voltage v dd characteristic with the main system clock operating. 2. 2t cy or 128/f x is set by setting the interrupt mode register (im0). 47 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) t sik2 100 ns serial transfer operation 2-wire and 3-wire serial i/o modes (sck ... internal clock output) parameter symbol conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 1600 ns t kcy1 3800 ns sck high- and low- v dd = 4.5 to 6.0 v t kcy1 /2-50 ns level width t kcy1 /2-150 ns si setup time (to sck - ) si hold time (from sck - ) so output v dd = 4.5 to 6.0 v 0 250 ns delay time t kso1 from sck 0 1000 ns 2-wire and 3-wire serial i/o modes (sck ... external clock input) parameter symbol conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 800 ns t kcy2 3200 ns sck high- and low- v dd = 4.5 to 6.0 v 400 ns level width 1600 ns si setup time (to sck - ) si hold time (from sck - ) so output v dd = 4.5 to 6.0 v 0 300 ns delay time t kso2 from sck 0 1000 ns note r l and c l are load resistance and load capacitance of the so output line, respectively. t sik1 150 ns t ksi1 400 ns t kl1 t kh1 r l = 1 k w , c l = 100 pf note t ksi2 400 ns t kl2 t kh2 r l = 1 k w , c l = 100 pf note 48 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) sbi mode (sck ... internal clock output (master)) parameter symbol conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 1600 ns t kcy3 3800 ns sck high- and low-level v dd = 4.5 to 6.0 v t kcy3 /2-50 ns width t kcy3 /2-150 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 output v dd = 4.5 to 6.0 v 0 250 ns delay time from t kso3 sck 0 1000 ns sb0, 1 from sck - t ksb t kcy3 ns sck from sb0, 1 t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns sbi mode (sck ... external clock input (slave)) parameter symbol conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 800 ns t kcy4 3200 ns sck high- and low-level v dd = 4.5 to 6.0 v 400 ns width 1600 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 output v dd = 4.5 to 6.0 v 0 300 ns delay time from t kso4 sck 0 1000 ns sb0, 1 from sck - t ksb t kcy4 ns sck from sb0, 1 - t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns note r l and c l are load resistance and load capacitance, respectively, for the sb0 and sb1 output lines. t ksi4 t kcy4 /2 ns t sik3 150 ns t ksi3 t kcy3 /2 ns t sik4 100 ns r l = 1 k w , c l = 100 pf note t kl4 t kh4 r l = 1 k w , c l = 100 pf note t kl3 t kh3 49 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) a/d converter (t a = C40 to +85 c, v dd = 2.7 to 6.0 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit absolute C10 t a +85 c 1.5 lsb accuracy note1 2.5 v av ref v dd note2 C40 t a < C10 c 2.0 lsb conversion time note3 t conv 168/fx m s sampling time note4 t samp 44/f x m s av ref 2.5 v dd v analog input voltage v ian av ss av ref v r an 1000 m w av ref current ai ref 0.7 2.0 ma notes 1. absolute accuracy excluding quantization error ( 1/2 lsb) 2. adm1 should be set according to the a/d converter reference voltage (av ref ) as follows: when the av ref is between 0.6v dd and 0.65v dd , either 1 or 0 can be set. 2.5 v 0.6 v dd 0.65 v dd v dd (2.7 to 6.0 v) av ref adm1 = 0 adm1 = 1 3. the time from conversion start instruction execution to conversion end (eoc=1) (40.1 m s : at f x = 4.19 mhz) 4. the time from conversion start instruction execution to sampling end (10.5 m s : at f x = 4.19 mhz) analog input impedance reference input voltage 50 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) ac timing test points (excluding x1 and xt1 inputs): clock timings: ti0 timings: 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points x1 input 1/f x t xl t xh v dd ?.5 v 0.4 v xt1 input 1/f xt t xtl t xth v dd ?.5 v 0.4 v ti0 1/f ti t til t tih 51 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) serial transfer timing 3-wire serial i/o mode: 2-wire serial i/o mode: sck t kcy1 t kh1 t kl1 input data output data t sik1 t ksi1 t kso1 si so t kso2 t kl2 t kh2 t kcy2 sck sb0,1 t sik2 t ksi2 52 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing t intl t inth int0,1,2,4 kr0-3 t rsl reset t ksb t sbl t sbh t sbk t kso3,4 t sik3,4 t ksi3,4 t kl3,4 t kh3,4 t kcy3,4 sck sb0,1 t ksb t kso3,4 t sik3,4 t ksi3,4 t kl3,4 t kh3,4 t kcy3,4 sck sb0,1 t sbk 53 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 2.0 6.0 v data retention supply current note 1 i dddr v dddr = 2.0 v 0.1 10 m a release signal setting time t srel 0 m s oscillation stabilization release by reset 2 17 /fx ms wait time note 2 t wait release by interrupt request note3 ms notes 1. current which flows in the on-chip pull-up resistor is not included. 2. the oscillation stabilization wait time is the time during which the cpu operation is stopped to prevent unstable operation at the oscillation start. 3. depends on the basic interval timer mode register (btm) settings (see the table below). wait time btm3 btm2 btm1 btm0 (figures in parentheses are for operation at fx = 4.19 mhz) 0 0 0 2 20 /fx (approx. 250 ms) 0 1 1 2 17 /fx (approx. 31.3 ms) 1 0 1 2 15 /fx (approx. 7.82 ms) 1 1 1 2 13 /fx (approx. 1.95 ms) data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) stop mode data retention mode stop instruction execution reset v dd internal reset operation halt mode operating mode v dddr t srel t wait stop mode data retention mode stop instruction execution v dd halt mode operating mode v dddr t srel t wait standby release signal (interrupt request) 54 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 11. characteristic curves (for reference only) i dd vs v dd (main system clock: 4.19-mhz crystal resonator) 3.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 0 2 4 6 8 (t a =25 ?) pcc=0011 pcc=0010 pcc=0000 main system clock halt mode + 32 khz oscillation subsystem clock operation mode main system clock stop mode + 32 khz oscillation and subsystem clock halt mode supply current i dd [ma] x1 x2 crystal resonator 4.19 mhz xt1 xt2 330 k w 22 pf crystal resonator 32.768 khz 18 pf 22 pf 18 pf supply voltage v dd [v] 55 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) i dd vs v dd (main system clock: 2.0-mhz crystal resonator) 3.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 0 2 4 6 8 (t a =25 ?) pcc=0011 pcc=0010 pcc=0000 main system clock halt mode + 32 khz oscillation subsystem clock operation mode main system clock stop mode + 32 khz oscillation and subsystem clock halt mode supply voltage v dd [v] supply current i dd [ma] x1 x2 crystal resonator 2.0 mhz xt1 xt2 330 k w 22 pf crystal resonator 32.768 khz 18 pf 22 pf 18 pf 56 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) i dd vs v dd (main system clock: 4.19-mhz ceramic resonator) 3.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 024 68 (t a =25 ?) pcc=0011 pcc=0010 pcc=0000 main system clock halt mode + 32 khz oscillation subsystem clock operation mode main system clock stop mode + 32 khz oscillation and subsystem clock halt mode supply voltage v dd [v] supply current i dd [ma] x1 x2 ceramic resonator 4.19 mhz xt1 xt2 330 k w 30 pf crystal resonator 32.768 khz 18 pf 30 pf 18 pf 57 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) i dd vs v dd (main system clock: 2.0-mhz ceramic resonator) 3.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 024 68 (t a =25 ?) pcc=0011 pcc=0010 pcc=0000 main system clock halt mode + 32 khz oscillation subsystem clock operation mode main system clock stop mode + 32 khz oscillation and subsystem clock halt mode supply voltage v dd [v] supply current i dd [ma] x1 x2 ceramic resonator 2.0 mhz xt1 xt2 330 k w 30 pf crystal resonator 32.768 khz 18 pf 30 pf 18 pf 58 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) i dd vs f x i dd vs f x 2.0 1.5 1.0 0.5 0 0 2 (v dd = 5 v, t a =25 ?) f x [mhz] i dd [ma] x1 x2 1 3 4 5 6 pcc=0000 main system clock halt mode 0.5 0.4 0.3 0.2 0.1 0 0 2 (v dd = 3 v, t a =25 ?) f x [mhz] i dd [ma] x1 x2 1 3 4 5 6 pcc=0000 main system clock halt mode pcc=0010 pcc=0011 40 30 20 10 0 0 2 (t a =25 ?) v ol [v] i ol [ma] 1 3 4 5 v dd =6 v v dd =5 v v dd =4 v v dd =3 v v dd =2.7 v 30 25 20 15 10 5 0 0 2 (t a =25 ?) v ol [v] i ol [ma] 1 3 v dd =6 v v dd =3 v v dd =5 v v dd =4 v v dd =2.7 v pcc=0010 pcc=0011 i ol vs v ol (port 0) i ol vs v ol (ports 2, 6) 59 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) i ol vs v ol (port 3) i ol vs v ol (ports 4, 5) 40 30 20 10 0 0 2 (t a =25 ?) v ol [v] i ol [ma] 1 3 4 5 v dd =6 v v dd =5 v v dd =4 v v dd =3 v v dd =2.7 v 40 30 20 10 0 0 2 (t a =25 ?) v ol [v] i ol [ma] 1 3 4 5 v dd =6 v v dd =5 v v dd =4 v v dd =3 v v dd =2.7 v 15 10 5 0 0 2 (t a =25 ?) v dd - v oh [v] i oh [ma] 1 3 4 v dd =6 v v dd =5 v v dd =4 v v dd =3 v v dd =2.7 v i oh vs v oh 60 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 12. package drawings 42pin plastic shrink dip (600 mil) item millimeters inches a b c f g h i j k 39.13 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. 0.17 15.24 (t.p.) 5.08 max. n 0.9 min. r 1.541 max. 0.070 max. 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.600 (t.p.) 0.007 0.070 (t.p.) p42c-70-600a-1 a c d g notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. d 0.50?.10 0.020 m 0.25 0.010 +0.10 ?.05 0~15? 0~15? +0.004 ?.003 +0.004 ?.005 m k n l 13.2 0.520 2) item "k" to center of leads when formed parallel. 42 1 22 21 l m r b f h j i remark the outline dimensions and materials of es versions are the same as for mass-produced versions. h 61 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 44 pin plastic qfp ( 10) n a m f b 33 34 22 l 44 1 12 11 23 d c p detail of lead end s q 55 g m i j h k p44gb-80-3b4-2 item millimeters inches a b c d f g h i j k l 13.6 0.4 10.0 0.2 1.0 0.35 0.10 0.15 10.0 0.2 0.535 0.039 0.039 0.006 0.031 (t.p.) 0.394 note m n 0.12 0.15 1.8 0.2 0.8 (t.p.) 0.005 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.014 0.394 0.8 0.2 0.031 p 2.7 0.106 0.535 13.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.008 ?.009 +0.004 ?.005 +0.008 ?.009 +0.017 ?.016 +0.017 ?.016 +0.008 ?.009 +0.10 ?.05 remark the outline dimensions and materials of es versions are the same as for mass-produced versions. h 62 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) 13. recommended soldering conditions solder the m pd75064, 75066, 75068 under the soldering conditions indicated below. for further information on the recommended soldering conditions, refer to information document "semi- conductor device mounting technology manual (iei-1207)" . for soldering methods and conditions other than those of recommended, consult nec. table 13-1. soldering conditions for surface mounting devices m pd75064gb- -3b4 : 44-pin plastic qfp (10 x 10 mm) m pd75066gb- -3b4 : 44-pin plastic qfp (10 x 10 mm) m pd75068gb- -3b4 : 44-pin plastic qfp (10 x 10 mm) m pd75064gb(a)- -3b4 : 44-pin plastic qfp (10 x 10 mm) m pd75066gb(a)- -3b4 : 44-pin plastic qfp (10 x 10 mm) m pd75068gb(a)- -3b4 : 44-pin plastic qfp (10 x 10 mm) soldering conditions peak temperature of package surface : 235 c, time : 30 seconds max. (210 c min.), number of reflow processes : 2 or less 63 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) table 13-2. soldering conditions for through-hole type devices m pd75064cu- : 42-pin plastic shrink dip (600 mil) m pd75066cu- : 42-pin plastic shrink dip (600 mil) m pd75068cu- : 42-pin plastic shrink dip (600 mil) m pd75064cu(a)- : 42-pin plastic shrink dip (600 mil) m pd75066cu(a)- : 42-pin plastic shrink dip (600 mil) m pd75068cu(a)- : 42-pin plastic shrink dip (600 mil) soldering method wave soldering (only leads) partial heating soldering conditions soldering bath temperature : 260 c max., time : 10 seconds max. pin temperature : 300 c max., time : 3 seconds max. (per pin) caution solder only the leads by means of wave soldering , and exercise care that the jetted solder does not come in contact with the package. 64 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) appendix a. development tools the following development tools are provided for the development of a system which employs the m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a). notes 1. available for maintenance only 2. the ie-75000-r-em is not installed in the ie-75001-r. 3. ver. 5.00/5.00a has the task swap function, but it cannot be used with this software. os for ibm pc the following products are supported as os for ibm pcs. os version pc dos tm ver. 5.02 to ver. 6.1 ms-dos ver. 3.30 to ver. 5.00 note1 , 5.0/v note2 ibm dos tm j5.02/v note2 notes 1. ver. 5.0 and later have the task swap function, but it cannot be used with this software. 2 . only the english mode is supported. remark for development tools supplied by third-party manufacturers, refer to 75x series selection guide (if-1027) . in-circuit emulator for 75x series emulation board for ie-75000-r or ie-75001-r emulation probe for all shrink dip versions of this series emulation probe for all qfp versions of this series. a 44-pin conversion socket ev-9200g-44 is contained in this product. prom programming equipment an adapter for connecting the pg-1500 to the m pd75p068cu/gb. host machines: pc-9800 series (ms-dos tm ver. 3.30 to ver. 5.00a note3 ) ibm pc/at tm (refer to os for ibm pc ) ie-75000-r note1 ie-75001-r ie-75000-r-em note2 ep-75068cu-r ep-75068gb-r ev-9200g-44 pg-1500 pa-75p008cu ie control program pg-1500 controller ra75x relocatable assem- bler hardware software h 65 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) appendix b. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to device document doc. no. user's manual ieu-1366 instruction quick reference application note iea-1296 75x series selection guide if-1027 documents related to development tool document doc. no. hardware ie-75000-r/ie-75001-r user's manual eeu-1416 ie-75000-r-em user's manual eeu-1294 ep-75068cu-r user's manual eeu-1429 ep-75068gb-r user's manual eeu-1428 pg-1500 user's manual eeu-1335 software ra75x assembler package user's manual operation eeu-1346 language eeu-1363 pg-1500 controller user's manual eeu-1291 other related documents document doc. no. package manual iei-1231 semiconductor device mounting technology manual iei-1207 quality grades on nec semiconductor devices iei-1209 nec semiconductor device reliability/quality control system electrostatic discharge (esd) test guide to quality assurance for semiconductor devices mei-1202 microcomputer-related product guide - third party products caution the contents of the documents listed above are subject to change without prior notice to users. make sure to use the latest edition when starting design. 66 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) [memo] 67 m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruc- tion of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recom- mended to avoid using insulators that easily build static electricity. semi- conductor devices must be stored and transported in an anti-static con- tainer, static shielding bag or conductive material. all test and measure- ment tools including work bench and floor should be grounded. the opera- tor should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with se miconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull- down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. pro- duction process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. m pd75064, 75066, 75068, 75064(a), 75066(a), 75068(a) ms-dos is a trademark of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of ibm corporation. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard: computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special: automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m4 92.6 |
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